The experiment

Can today's AI design a whole mixed-signal chip?

An experiment: from a published PLL paper to a clean sky130 layout, driven end-to-end by agentic AI.

Input: one IEEE paper PDK: SkyWater sky130 (open) Tools the AI drove: ngspice · Magic · netgen · KLayout Effort: ~2 weeks, one supervising engineer

PLLTOP_AnaCore — the analog PLL loop core laid out on sky130 by AI, cap banks excluded. — The analog PLL loop core — **PLLTOP_AnaCore** — laid out on sky130 by AI, cap banks excluded: PFD, charge pump, loop filter, gm-C, dual-control ring VCO, regulator and ÷M feedback.

Why we ran this

This project had one question: how much of a full mixed-signal chip can today's agentic AI models actually design — and where do they get stuck? We wanted to find the real roadblocks and, more importantly, work out how to get AI past them. This is an exploration of capability, not a product.

We gave the AI a single input — a published PLL paper — and then tried to let it do everything after that: understand the circuit, size it, simulate it, lay it out, and clean it up.

The setup

Input. "An Improved CMOS Ring-Oscillator PLL," S. Williams, H. Thompson, M. Hufford, E. Naviasky, IEEE CICC 2004 (IEEE Xplore) — a dual-control ring-oscillator PLL, originally in a 0.18 µm CMOS process.

Target & tools. We retargeted it to the open-source SkyWater sky130 PDK. The AI drove the standard open EDA stack itself: ngspice for simulation, Magic for DRC and parasitic extraction, netgen for LVS, and KLayout for GDS — all against sky130 models and rules.

Where AI is already strong

Working from the paper, the AI handled the front of the flow well, largely on its own. It:

built the device-level netlists,
sized and optimized transistors to meet the targets,
ran ngspice simulations and interpreted the results,
wrote its own documentation and status notes, and
iterated — change a value, re-simulate, check, repeat.

Circuit reasoning — topology, spec intent, "this corner isn't hitting the target, adjust that" — is genuinely a strength. This part felt like working with a fast, tireless junior designer.

The roadblock: layout

Layout is where out-of-the-box AI falls down. Ask a model to emit GDS polygons directly and it produces shapes that short, break spacing rules, or drift off-grid. Layout is spatial, and text-trained models are weakest there.

What worked was indirection through a generator: the AI doesn't draw the layout — it writes a Python generator that draws the layout. The AI reasons in code ("place this bank, mirror it, route this net on this layer"), which plays to its strengths, and the generator turns that intent into geometry.

Underneath the generator sits a collision-aware placement and routing engine — the grid tracks what is free, blocked, or already used, so the generated GDS is legal by construction and the whole class of "two shapes overlapped" errors mostly cannot happen. The AI also improved this GDS-generation tooling itself, building on existing open-source layout approaches rather than starting from a blank page.

PLLTOP4_D40 — the delivered analog PLL macro: loop core plus three MIM cap banks and an on-macro ÷40, on sky130. — What the generator produced: the delivered analog macro **PLLTOP4_D40** — the loop core (bottom-left) plus three MIM cap banks and an on-macro ÷40, assembled into the chip.

The real lesson: AI needs to know how well it's doing

The single biggest factor in making this work: AI performs dramatically better when it has a way to measure itself.

DRC and LVS pass/fail reports, on their own, were not enough. Handed a raw violation log, the AI would flail — the reports say what is wrong in tool-speak, not why or what to change. To debug efficiently it needed richer feedback:

rendered images of the layout that the AI looks at and reasons about visually,
structured, categorized verdicts that turn a violation into an actionable symptom, and
a numeric quality score, so "better" and "worse" are measurable rather than guessed.

With those feedback loops in place, the AI did the complete back end — placement, routing, and full DRC/LVS cleanup — with no human intervention. That is the result we care about most.

A whole chip, not just a block

The assembled mixed-signal chip pll_chip on sky130 — pad ring and fill around the PLLTOP4_D40 analog macro and the digital control core. — The assembled mixed-signal chip **pll_chip** (1.90 × 1.90 mm) on sky130 — a full pad ring and metal fill around the analog PLL macro PLLTOP4_D40 (left) and the digital control core pll_dcc (centre-right).

The analog PLL core is the hard part, but the point of the experiment was breadth — so the AI ran the surrounding flow too, from design through chip-level signoff:

Digital control block — RTL synthesis, multi-corner static timing analysis (setup/hold across slow/typical/fast corners), clock-tree synthesis, and scan/DFT insertion, hardened to a placed-and-routed, timing-clean macro.
Chip top level — a pad ring from the IO cell library, pad placement, the core power ring, metal fill, and assembly of the analog and digital macros into one chip, checked to DRC and LVS.
Extraction & closure — RC parasitic extraction, post-extraction (post-layout) simulation, and, wherever a spec came up short, the AI modified the design (resize / re-bias) and re-ran until it closed.
Mixed-signal modeling — a real-number (RNM) behavioural model of the analog PLL, so the full chip — analog plus digital — can be simulated functionally and fast.
Human-readable views — a schematic and a symbol generated from the netlist, so engineers can read, review, and sign off on what the AI built.

The takeaway isn't one clever block — it's how much of the whole chain (synthesis, timing, clock tree, IO, fill, assembly, extraction, modeling, and review views) the AI could carry, with a human only supervising.

How close did it get?

A few top-level numbers, paper vs. this AI-built sky130 layout:

Parameter	Paper (0.18 µm)	This work — sky130, AI
Process	0.18 µm CMOS	sky130 (open PDK)
Reference → output	27 MHz → 270 MHz (÷10)	270 MHz lock (all corners)
VCO tuning range	100–500 MHz (5:1)	100–300 MHz (3:1), no band switching

The final post-layout results are complete and consistent — all three corners lock at 270 MHz, with period jitter under 5 ps:

Corner	Lock	Period jitter (ps)
TT	270 MHz	1.96
SS	270 MHz	0.60
FF	270 MHz	2.30

TT post-layout lock witness — the VCO frequency settles to 270 MHz, the control voltages settle, and the digital lock_detect asserts. — TT post-layout lock witness — the analog loop (ngspice) and the digital `lock_detect` (Verilog) co-simulated on one time axis: the VCO is pulled to 270 MHz, the control voltages settle, and the digital detector witnesses the lock.

The layout is DRC-clean and LVS-matched. And because the flow is PDK-parameterized, the same process ports to another open-source PDK in about a day — most of that is re-pointing at new design rules and device models, not re-doing the design.

Open-sourced: the Paper-to-Chip repository

We've open-sourced this design. The complete generated artifacts — the chip and macro GDS, behavioural + real-number (RNM) models, schematics and symbols, the signoff reports (DRC / LVS / timing / lock-detect), and the docs — are published under a permissive MIT license:

→ github.com/NavinSiHive/Paper-to-Chip

We're releasing it because open silicon deserves open, worked examples. Whether you're a student learning mixed-signal design, an individual or hobbyist exploring sky130, a researcher benchmarking AI-for-EDA, or a startup looking for a proven PLL starting point — you're welcome to study it, simulate the models (they run in ~2 minutes), reuse the blocks, adapt it to your own project, or build on top of it. The one thing we've held back is the proprietary layout engine that generated the macro; the design it produced is all there.

If it helps you build something, we'd love to hear about it.

What this is — and isn't

This started as an experiment, not a commercial product — a way to see how far current agentic AI can go in mixed-signal chip design, and to find the machinery that unblocks it.

The takeaway: with the right scaffolding — generators instead of raw polygons, collision-aware geometry, and above all good feedback — today's models can already take a real block from paper to clean layout, autonomously.

Think of AI video generation. In early 2023, the state of the art was a now-infamous clip of Will Smith eating spaghetti — grainy, warping, his face melting into the noodles. Barely two years later, AI video is near-photorealistic. This chip is our grainy-Will-Smith-eating-spaghetti moment — unmistakably early and imperfect, but at the start of a curve that, in every adjacent domain, has bent upward astonishingly fast.

As the models improve, and as engineers get better at wielding them, we expect much larger chips to be fully AI-developed. We're now working on exactly that — bigger chips, ourselves.

We at Si-Hive are passionate about AI and analog design — 40+ years of analog design experience and 5+ years in AI. We're looking for analog / mixed-signal / chip-design partners and pilots. Our flow runs today on open-source PDKs, and we're keen to bring it to your commercial or foundry PDK as a partner.

Build something with it — or with us

This isn't about reducing engineers — it's about giving today's and tomorrow's engineers better work. By handing the repetitive 80–90% to AI, we want to unfold analog / mixed-signal block and chip design, so engineers spend their days inventing, not repeating.

Explore Paper-to-Chip on GitHub Talk to us