Milestone · from-scratch autonomous layout

Planar 130 nm → 7 nm FinFET: a whole PLL, signed off hands-off

Last week we open-sourced a ring PLL on SkyWater's 130 nm planar CMOS. This week the same engine re-architected it onto a 7 nm FinFET node, brought its bias on-chip, and wrapped it into a full, physically-verified mixed-signal chip — with on-chip lock witnessed across every corner. All autonomous; all model-grade on a predictive PDK.

Node: sky130 → ASAP7 (7 nm FinFET) Result: 5.0 GHz all PVT · self-contained macro → full signed-off chip · on-chip lock witnessed Effort: ~4 days, autonomous ★ PDK: ASAP7 — predictive academic, not silicon

Read this first — honest by construction ASAP7 is the standard academic predictive FinFET PDK — not silicon-calibrated, not manufacturable. The numbers below are model-grade, from committed simulations. This is a design-automation and closed-loop-signoff demonstration on a representative 7 nm node — not a tapeout, not a silicon result. The breakthrough is the automation, not FinFET (a mature technology). Our sky130 work remains the real, manufacturable, planar leg.

The packed ASAP7 PLL top layout — a VDD/VSS power grid with the loop-filter capacitor, regulated VCO, charge pump, divider, PFD and level-shifter placed and outlined. — The signed-off ASAP7 PLL top, auto-packed to **2045 µm²** (−48% from a sparse 3960 µm² first pass): loop-filter cap and regulated VCO up top, the charge pump / PFD / divider cluster bottom-right, caps placed adjacent to their recipient cells. DRC-0-net-new, LVS-match.

From last Monday's sky130 PLL

A few days ago the story was a dual-control ring PLL on SkyWater sky130 — 270 MHz, DRC-clean, LVS-matched, open-sourced. That's the manufacturable, silicon-credible anchor. The question we set ourselves next: is the engine tied to that node, or is a node just a plugin?

So we pointed CAL — our from-scratch, config-less, collision-aware grid-layout engine — at a 7 nm FinFET node and asked it to bring the same PLL across. Not a shrink of the old GDS; a genuine re-design for a new device physics and a 0.7 V rail. It did the device generation, floorplan, routing, DRC/LVS and closed-loop PVT signoff on its own, in about four days.

The headline port

18.5×

PLL frequency, node-jumped

The 270 MHz sky130 ring re-emerged at 5.0 GHz on 7 nm FinFET — a re-architecture, not a shrink.

PDK reach

PDKs, one plugin each

sky130 · gf180 · ihp130 (planar, silicon-real) + ASAP7 (7 nm FinFET).

Mixed-signal IP

LVDS versions on sky130

Four architectural iterations (v1–v4) of an LVDS transceiver, DRC/LVS-clean, on the same engine.

A re-architecture, not a shrink

7 nm at 0.7 V has no headroom for the sky130 topology. The engine's decisions, made autonomously:

VCO supply: dropped the sky130 series regulator (no 0.7 V headroom) for an on-rail LDO — the dropout moves into the supply path so the current-starved ring can stay two-transistors-high. That's what recovers supply rejection at 0.7 V.
Decoupling = 6.7 pF: the clean, well-damped, best-jitter / 8×-PSRR operating point. Smaller decaps were ruled out (an under-damped dead zone and a jitter anomaly); jitter is charge-pump/PFD-limited, so more decap only buys open-loop PSRR.
GmStage removed: architecturally moot once the regulator is a rail LDO rather than a Gm-C — so the top carries no vestigial block.

The measured spec sheet

RC-extracted top, per PVT corner (TT / SS / FF). Every figure is a committed simulation result.

Spec	TT	SS	FF	How it was measured
Lock @ 5 GHz	5.001	4.999	5.003	GHz — locks from reset, every corner
Jitter, rms	0.105	0.122	0.124	ps, intrinsic; 0.340 ps under a 20 mV / 30 MHz supply-ripple stress
Reference spur	−56.1	−53.1	−63.0	dBc — the faithful charge pump's matching
Phase margin	57.6°	57.1°	59.9°	multi-tone jitter-transfer (exact); every corner well-damped
Open-loop PSRR	8.3× (K_vdd 115 MHz/V @ 50 MHz)			on-rail LDO, 6.7 pF
Lock / capture range	[ 4.5 , 6.2 ] GHz worst-case			5 GHz sits inside with margin
Cold-start acquire	✓ all PVT, both sides			loop pulls VCTRL from reset on its own
Top DRC / LVS	0 net-new real · MATCH (6 blocks / 13 nets)			analog transistor-LVS'd; no vestigial GmStage

From-reset lock acquisition across PVT: VCTRL settles and the VCO frequency converges to the 5.0 GHz target for TT, SS and FF. — From-reset acquisition, all three corners: the control voltage settles and the VCO pulls to the 5.0 GHz target on its own — no seeded operating point required.

One point worth stating plainly: the −48% auto-pack didn't cost performance — it improved it. The tighter floorplan shortened the loop-critical control (VCTRL) route by 64%, which dropped worst-case jitter from 0.161 to 0.124 ps and worst-case spur from −49.7 to −53 dBc (all three corners still lock at 5.0 GHz). Packing made the PLL better, not just smaller.

sky130 → ASAP7, honestly

Same PLL, two nodes. Where 7 nm plus the engine's decisions genuinely win — and the one row where they don't.

Metric	sky130 PLL (real)	ASAP7 PLL (this work)	Verdict
Output frequency	270 MHz	5.0 GHz	18.5× higher
Jitter, worst corner (FF)	2.74 ps	0.124 ps	22× lower, absolute
Phase margin, worst (FF)	16° under-damped	59.9° well-damped	no weak corner
Reference spur	−52 … −75 dBc	−53 … −63 dBc	on par — sky130's best wins

Spurs are comparable — we do not claim to beat sky130 there; its best corners are better. The wins we do claim are frequency, worst-case jitter, and the absence of an under-damped corner.

When the fast method lied

Phase margin is the row worth dwelling on — because getting it right almost didn't happen. The quick phase-step method read 71° / 66° / 34° across TT / SS / FF, which would have flagged FF as a dangerously under-damped corner needing a fix.

It was wrong — in both directions. The exact multi-tone jitter-transfer method (the same gold standard we trust on sky130) measured 57.6° / 57.1° / 59.9° — every corner well-damped, peaking under 1.8 dB. The phase-step had over-read TT (71° vs 58°) and under-read FF (34° vs 60°). The "weak corner" was a measurement artifact, not a design flaw. No lever was needed — but only the rigorous method could tell us that. Trusting the fast approximation would have sent the engine chasing a problem that wasn't there.

From a PLL top to a full chip

Everything above — the spec sheet, the comparison — was measured with idealized bias sources. Fair for a closed-loop demo, but not a self-contained macro a chip could drop in. So the flow made it real: it replaced those ideal sources with real, on-chip bias generation and made the macro self-starting — a minimal 5-port interface (VDD, VSS, REFCLK, PLL_CLK, FBCLK) with no external bias, reset or enable pads, DRC/LVS-clean at ≈ 62 × 35 µm, locking 5.0 GHz from a dead power-on ramp.

Honestly, bringing the bias on-chip surfaced a real analog finding: the on-chip bias doesn't track across PVT as tightly as the ideal source it replaced, so the slow and fast corners degrade (the 5.0 GHz lock still holds at every corner). It's the classic ring-PLL tracking issue — being closed with textbook self-biasing, partial recovery already in hand and full recovery scoped. We'd rather show you that than hide it.

That self-contained macro is now wrapped into a full mixed-signal chip. PLL_CHIP_ASAP7 — 233 × 137 µm (0.032 mm²) — surrounds the analog PLL top with a chip-side digital control core, an I/O pad ring, ESD, a seal ring, decap and an M8/M9 VDD/VSS power mesh, and exposes a pad-safe divide-by-100 output: 50 MHz from a 500 MHz reference. At the chip level it is DRC 0-net-new, LVS match-uniquely (the analog top and the digital lock detector included), antenna-0, connectivity clean.

The assembled ASAP7 7 nm mixed-signal chip PLL_CHIP_ASAP7 — the analog PLL top inside an I/O pad ring, ESD, seal ring, decap and a VDD/VSS power mesh, with the digital control core. — The assembled 7 nm chip — **PLL_CHIP_ASAP7**, 233 × 137 µm — wrapping the self-biased analog PLL top and the digital control core in a full pad ring, ESD, seal ring, decap and power mesh. Chip DRC-0-net-new, LVS match-uniquely, antenna-0.

On-chip lock, witnessed across corners

The digital control core (pll_dcc_asap7, 18 × 18 µm) is a frequency-counter lock detector plus a divide-by-10 observation divider — an MVP that is lock-detect and divider only (SPI/CSR and scan/DFT are noted as future adds, not built). It was co-simulated against the real analog loop — real on-chip bias, full-RC — at all three corners.

At each corner the loop reaches ~5.0 GHz, the ÷10 feedback returns 500 MHz to match the reference 1:1, and the detector raises LOCK well inside the stable region: FF 5.006 GHz (LOCK at 850 ns), SS 4.999 GHz (LOCK at 811 ns), TT ~5.0 GHz. The digital timing closes 500 MHz at every corner.

Chip-level co-simulation: the digital lock detector asserts LOCK while the real analog loop settles to 5.0 GHz and the divide-by-10 feedback matches the 500 MHz reference. — On-chip lock witnessed against the *real* analog loop (typical corner shown). The detector raises LOCK inside the stable region at all three corners — FF 5.006 GHz @ 850 ns, SS 4.999 GHz @ 811 ns, TT ~5.0 GHz.

What "physically verified" means here — and doesn't The analog is a full-custom, real transistor-level FinFET layout that passes real DRC and transistor-level LVS. The digital is a real place-and-route and timing flow on mock standard cells (route-DRC-0 and STA-clean — not transistor-LVS). The pad ring, ESD and seal ring are demonstrational: ASAP7 ships no I/O or ESD library, and there is no TLP / HBM / CDM. Physically verified, yes; tapeout-ready, no — and on a predictive PDK, not silicon. That distinction is the point.

Any PDK is one plugin

None of this is bespoke to 7 nm. A design is written once, PDK-agnostically; each process plugs in behind a contract that either passes Pdk.check() or tells you exactly what's missing. Four PDKs live behind it today — sky130, gf180, ihp130 (planar, silicon-real) and ASAP7 (7 nm FinFET) — with a cross-PDK invariant regression suite.

The FinFET port also built reusable machinery that any FinFET PDK inherits: fin quantization, ≤12-fin folding, series-stacked long-L devices, BSIM-CMG through OSDI, latch-up taps and RC extraction. That machinery is what makes the next node a plugin rather than a rebuild.

The path we've actually paved

130 nm

sky130 · planar

Silicon-real · done

PLL + 4× LVDS, DRC/LVS-clean, manufacturable open PDK — a real tapeout path.

7 nm

ASAP7 · FinFET

Predictive · done

PLL signoff → self-contained macro → a physically-verified full chip with on-chip lock. Outputs open-sourced.

7 nm

commercial · FinFET

A plugin away

TSMC N7 / Samsung / Intel are the same FinFET flow behind an NDA. The gate is access, not capability.

2–1 nm

GAA · nanosheet

Projected

The engine and porting contract carry over; the device generator extends FinFET → gate-all-around. Methodology paved; GAA models are the added work.

The honest ledger

✓ What we claim

18.5× frequency at 22× lower worst-case jitter — both from committed sims.
Well-damped every corner (57–60°) by the exact jitter-transfer method.
DRC-0-net-new + LVS-match top, no vestigial blocks, RC-extracted-then-reduced netlist throughout.
4 PDKs, one plugin each — planar and FinFET, with a cross-PDK regression suite.
Area auto-packed −48% (3960 → 2045 µm²), caps adjacent to recipients.
A self-contained, self-starting macro — bias on-chip, no external bias/reset/enable pads.
A physically-verified full chip (PLL_CHIP_ASAP7, 233 × 137 µm) — chip DRC-0-net-new, LVS match-uniquely, antenna-0.
On-chip lock witnessed at all three corners against the real analog loop.

△ What we do not claim

Not silicon. ASAP7 is predictive — numbers are model-grade, not measured on a wafer.
Not better spurs than sky130 — they're comparable; sky130's best corners win.
Commercial 7 nm is NDA-access-gated, not capability-gated.
1–2 nm needs GAA device models — the framework carries, the transistor generator extends.
The breakthrough is the automation, not the FinFET — we advanced neither the device nor the process.
Not tapeout-ready. The pad ring, ESD and seal ring are demonstrational — no ASAP7 I/O / ESD library, no TLP / HBM / CDM.
Digital on mock standard cells — a real P&R + STA flow (route-DRC-0 + timing), not transistor-LVS.
On-chip bias not yet PVT-flat — the real bias degrades the slow / fast corners; recovery is in progress.

We at Si-Hive are passionate about AI and analog design — 40+ years of analog design experience and 5+ years in AI. We're looking for analog / mixed-signal / chip-design partners and pilots. Our flow runs today on open-source PDKs, and we're keen to bring it to your commercial or foundry PDK as a partner.

Build something with it — or with us

This isn't about reducing engineers — it's about giving today's and tomorrow's engineers better work. By handing the repetitive 80–90% to AI, we want to unfold analog / mixed-signal block and chip design, so engineers spend their days inventing, not repeating.

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