AI-Driven Mixed-Signal Chip Design
New The flow now catches what DRC and LVS can't: EM/IR, per cell, at build timeSi-Hive uses agentic AI to drive the entire flow — circuit design, analog layout, digital synthesis, chip assembly and DRC/LVS signoff — turning a datasheet or a research paper into clean, verified silicon.
Proof, not slideware
An EM/IR reliability gate now runs beside DRC and LVS on every cell the engine builds. The newest capability leads below; the full 7 nm chip milestone and the manufacturable sky130 anchor follow in detail.
A layout can pass every conventional check and still cook its own metal. 102× → 2.65× in 7 automated iterations — a from-scratch 20 mA driver, measured against its own operating current, repaired through the builders, DRC/LVS re-gated at every step. The EM/IR gate now rides every cell build.
Honestly: sky130 EM limits are estimates (SkyWater publishes none) — these are structural findings, not signoff; ihp130/gf180 run on real foundry LEF limits. None of this replaces foundry signoff — it moves discovery to the cheapest moment.
The self-contained, on-chip-biased macro was wrapped into a full mixed-signal chip — PLL_CHIP_ASAP7 (I/O pad ring, ESD, digital control core, power mesh) — and on-chip lock was witnessed across all three corners against the real analog loop.
Honestly: ASAP7 is a predictive PDK — physically verified but demonstrational, not tapeout-ready. The on-chip bias surfaced a PVT-tracking finding we're closing.
Read the full Paper-to-Chip (sky130) story →
Circuit reasoning is already a strength. Working from the paper, the AI built the device-level netlists, sized and optimised the transistors, ran ngspice, wrote its own documentation and iterated — like a fast, tireless junior designer.
Layout is the roadblock — so we changed the game. The AI doesn't draw polygons; it writes a Python generator that draws them, on a collision-aware grid that is legal by construction. And the multiplier: the AI can measure itself — rendered images it reasons about visually, structured verdicts, and a numeric quality score. With those loops it did the complete back end — placement, routing, and full DRC/LVS cleanup — with no human in the loop.
One supervising engineer. One paper in. A whole chip out — analog PLL macro, digital control core, pad ring, fill and assembly, checked to DRC and LVS.
Paper (0.18 µm) vs. this AI-built sky130 layout — post-layout, RC-extracted.
| Parameter | Paper (0.18 µm) | This work — sky130, AI |
|---|---|---|
| Process | 0.18 µm CMOS | sky130 (open PDK) |
| Reference → output | 27 MHz → 270 MHz (÷10) | 270 MHz lock (all corners) |
| VCO tuning range | 100–500 MHz (5:1) | 100–300 MHz (3:1), no band switching |
Layout is DRC-clean and LVS-matched. Because the flow is PDK-parameterised, the same design ports to another open PDK in about a day.
Final RC-extracted rides, TT / SS / FF. Complete and valid.
| Metric | TT | SS | FF |
|---|---|---|---|
| Lock frequency | 270 MHz | 270 MHz | 270 MHz |
| Period jitter | 1.96 ps | 0.60 ps | 2.30 ps |
Every corner locks at 270 MHz with period jitter under 5 ps — the final post-layout rides are valid and complete.
We've open-sourced this PLL as the Paper-to-Chip repository — netlists, device sizing, the sky130 layout generators, review schematics, and the full paper-to-clean-silicon flow. It's there for everyone: students learning how mixed-signal design and layout actually work, individual engineers and hobbyists exploring open silicon, university groups, and startups who want a PLL to build on. The 7 nm FinFET outputs are open too — see the ASAP7 Planar-to-FinFET repository.
How it works
Whether you have a vendor datasheet or a research paper, our AI pipeline turns a specification into verified silicon — analog blocks or whole mixed-signal chips.
Hand us a datasheet or target spec. The engine derives topology, sizes devices, generates layout, and converges to DRC/LVS-clean GDS across PVT corners.
Turn a published architecture into an implementable, PDK-portable block — or a whole mixed-signal chip, analog and digital assembled together.
Building blocks
Core building blocks — plan to generate and verify with AI, then ready to integrate into your SoC or to compose into a full chip.
Ring & LC VCOs, PFDs, charge pumps, loop filters, dividers
SAR, pipeline, and delta-sigma architectures from spec targets
Current-steering and resistor-ladder DACs with matching optimisation
CTAT/PTAT references, curvature correction, low-drift BGR cores
Low-dropout regulators with stability and load-transient optimisation
Buck/boost converters, references, and PMIC building blocks
Memory PHY heritage — GDDR, LPDDR, HBM, DDR
Any topology from your datasheet or paper, plus the digital control around it
Process nodes
Our flow is PDK-parameterised, so every design is portable — same spec, multiple foundries. Three open planar nodes are live today, joined by a predictive 7 nm FinFET port (ASAP7); commercial and foundry PDKs on request.
Have silicon on a commercial or foundry PDK? The design rules and device models change — the design doesn't. We'll bring the whole flow to your process, with you. That's exactly the partnership we're looking for.
Where this is going
A design is written once; a process is a plugin. Here's the path we've actually paved — and where it goes next. sky130 is real, manufacturable silicon; ASAP7 is a predictive 7 nm demonstration. Early — like AI video's "grainy Will Smith" phase — but on a curve that, in every adjacent field, bends upward fast.
A ring PLL plus four LVDS iterations, DRC/LVS-clean on a manufacturable open PDK. A real tapeout path.
The same PLL re-architected and signed off — 5.0 GHz, well-damped every corner. ASAP7 is a predictive academic PDK, not silicon.
TSMC N7 / Samsung / Intel are the same FinFET flow behind an NDA. The gate is access, not capability.
The engine and porting contract carry over; the device generator extends FinFET → gate-all-around. GAA models are the added work.
About Si-Hive
We at Si-Hive are passionate about AI and analog design — 40+ years of analog design experience and 5+ years in AI. Founded in 2020, Si-Hive Technologies pairs decades of high-speed mixed-signal know-how with an AI-native layout and optimisation engine.
We've delivered first-silicon-success PHY designs at GDDR6 (18 Gbps), HBM2/2e, DDR3/4 and LPDDR3/4/5 — and now we bring that rigor to AI-driven mixed-signal chip design.
Recent milestones — AI-driven
Get in touch
We're looking for analog / mixed-signal / chip-design partners and pilots. Our flow runs today on open PDKs, and we'd love to bring it to your commercial or foundry PDK. If you have an analog or mixed-signal block or chip (< 10 mm²) you'd like to build with AI, let's talk.