Capability · a third gate beside DRC and LVS

DRC clean. LVS clean. 102× over its electromigration limit.

A brand-new 20 mA switching driver came out of our flow DRC-clean and LVS-matched on its very first build — by every conventional check, done. Then the flow's newest gate measured the metal against the cell's own current and found it 102× over its electromigration limit, with 156.7 mV of IR drop against a 32.4 mV budget. A layout can pass everything and still cook its own metal. Our flow now catches that at generation time — and repairs it.

The build that passed everything

SwitchDriver20 is a cell class our flow had never seen: a segmented push-pull power switching driver on sky130 (1.8 V; output stage W_P = 400 µm / W_N = 128 µm in 10 segments each, tapered break-before-make predriver, core 93.9 × 13.2 µm), designed and laid out from scratch after the new gate was deployed. Its first build came out DRC = 0 and LVS "match uniquely" with zero healing iterations — rail widths and via habits any designer would start with. By every check the industry gates cells on, this layout was finished.

Then the EM/IR tier ran. It didn't ask for a current estimate — it ran the cell's own testbench (10 MHz, ~50 % duty into 12 Ω → 0.9 V + 5 pF) and measured 20.67 mA (VDD) / 22.67 mA (VSS) average per rail, 45/46 mA peaks. Screened against those measured currents at the worst-case corners, the verdict on the "finished" layout:

FAIL: worst EM 102.25× — a single via3 stud carrying the entire 22.67 mA — worst IR-drop 156.7 mV against a 32.4 mV budget, 704 gating violations plus 572 review rows, and 20 machine-readable repair directives. Gate wall time: 14.8 s, including the 12.9 s live current measurement.

Where this came from — credit where it's due

The initial inspiration was Kevin Cameron's. We came across his work on electromigration screening — an EM tool that reads a layout's parasitics, tracks each wire's current density through the simulation, and copies the segments that need attention onto their own layers so they are easy to see — and it set us thinking about making EM and IR-drop a first-class, per-cell check inside our own layout flow.

Our engine — emirtool — was then written clean-room, with no code reused, and extended with the parts that had no counterpart in the original: the IR-drop nodal solver, supply-short detection, rectangle-graph extraction with via-landing splitting, the repair-directive schema and the layout-engine closed loop, PVT corner derating, the gf180/asap7 tech packs, and the test infrastructure. Thank you, Kevin.

The proof, on real foundry rules: a dual-control VCO rebuilt in IHP 130 nm

Everything above runs on sky130, which publishes no EM rules — so those findings are structural: they rank and localize risk, they do not sign off. To put that same gate on real foundry rules, we are rebuilding one of our analog cells — a dual-control ring VCO — from scratch in IHP's open 130 nm process, and running it through the EM/IR gate at IHP's real foundry current-density limits: the DCCURRENTDENSITY values shipped in the sg13g2 tech LEF, not estimates. That distinction is the whole point — sky130 has no published EM rules, so those results are structural; ihp130 ships real LEF DCCURRENTDENSITY, so the before/after numbers below are signoff-grade, screening the foundry's own physics.

Result — measured, real foundry limits. Both v1 and v2 are DRC-0 and LVS-match in ihp130, screened against IHP's real LEF DCCURRENTDENSITY at a 1.0× signoff gate. A habit-sized first build failed at 3.37× its EM limit on the thin VSS supply straps; one automated repair iteration brought it to a signoff-grade pass. Full before/after reports, heat maps and directives: EMIR-Aware-Layout-Engine repository.

What we built: a third gate, a repair loop, a learning loop

DRC and LVS qualify a layout as geometrically legal and correctly connected — they say nothing about whether the metal survives the current it will actually carry, so a 0.14 µm strap feeding half a milliamp passes both without comment. EM and IR-drop are conventionally checked at chip-level signoff, days or weeks after the geometry was created — or discovered at silicon. Inside our CAL layout engine, emirtool now runs at three levels:

cell builders ──► build GDS → DRC → LVS → EM/IR GATE (0.03–0.27 s)
                  one verdict: clean only if ALL gates pass
                        │ GDS (or any RCX tool's SPEF + geometry sidecar)
                        ▼
                  emirtool: rect-level extraction → IR nodal solve → EM screen
                  at nominal + worst-case corners (derates stamped in the report)
                  out: report {json,md,csv} · per-rect heat map · repair directives
                        ▼
                  repair loop: mesh ladder L0→L3 → rebuild → DRC/LVS → re-analyze
                  auto BEFORE_AFTER · terminal = CLEAN | PLATEAU | UNACTIONABLE | MAX_ITER
                        ▼
                  learning loop: 430 harvested directives → 57 recurring patterns
                  → builder-default proposals + ledger lessons wired into the builders

Every net is decomposed into rectangles split at via landings, so each narrow neck gets its own EM width and the resistor network is actually solvable; the IR solve is validated against ngspice DC to under 1 µV. Above the per-cell fixes sits the learning loop: a curator harvested 430 directive records from 48 artifact files across 18 designs and 4 PDKs and distilled them into 57 recurring patterns, published as builder-default proposals — so the same violation stops being generated at all. Four PDKs are live behind honest provenance: ihp130 and gf180 with real foundry LEF limits; sky130 and asap7 with clearly-labeled estimates.

Proof on the flow's own cells: the bug LVS couldn't see

Before the forward test, the gate was pointed at cells that already existed. VCO_REG — the sky130 regulator + VCO island from our PLL — was freshly built and verified: DRC = 0, netgen LVS "circuits match uniquely", structural gate PASS. The current-aware analysis at its measured operating point (841/846 µA rails, 444 µA internal VCO supply) then found the regulator island handing the entire 444 µA through a single 0.14 µm met1 column — worst EM ratio 7.07× at the worst-case corner in the solver's loop-boundary model (design arithmetic: 4.40× nominal → 6.95× at the corner), and V_VCO IR-drop of 37.1 mV against a 32.4 mV budget — the only IR violation in the whole VCO family. Connectivity was correct; the strap was merely undersized. No other check in the flow could see it.

The fix went through the cell builders, EM-sized from the tool's own directives — and the flow protected the repair itself. Attempt 2's patch reached 0.21 µm onto an adjacent gate strap, creating a DRC-legal short: DRC passed, and the flow's own LVS gate caught it (21 nets vs 22) in the same run, before any artifact left the working directory. Attempt 3 grew the other way with 0.15 µm clearance:

Nominal-clean is not signoff-clean

EM and IR are worst-case checks, so the flow treats the corner pair — 125 °C at VDD +5 % (EM) and VDD −10 % (IR), worst-RCX — as a first-class scenario and prints the derate factors it used: EM limits shrink to ×0.6335 (sky130), ×0.6157 (asap7), ×0.5398 (ihp130), ×0.6707 (gf180) at 125 °C. Our ChargePump, at its real 193 µA operating current, holds a comfortable-looking 1.77× EM margin at nominal — and only 1.12× at the signoff corner; the gap is exactly the sky130 derate. The campaign's genuinely corner-only failures — the kind a typical-corner flow ships — included an IR wall that passes at nominal (21.8 mV vs a 36 mV budget) and violates at the corner (34.3 mV vs 32.4 mV), an asap7 scenario over budget only at the IR corner (13.79 mV vs 12.6 mV), and EM rows legal at nominal (0.85×, 1.29×) that become violations at the corner (1.34×, 2.03×).

The forward test: v1 → v2, seven automated iterations

Back to the driver. The repair used both arms of the flow. The automated mesh loop ran 3 iterations (L0→L3, DRC/LVS re-gated clean at every level, IR 156.7 → 51.1 mV) and then reported its honest terminal — UNACTIONABLE, binding geometry below the mesh plane — matching a lesson the flow had already learned on ChargePump. The remaining directives mapped onto the builder's parametric power geometry: 4 rounds, during which the gate caught its own repair twice — round 1 introduced a 25 nm OUT↔VSS pad-into-rail merge that netgen LVS passed but the structural tier's connectivity check failed, and a stubborn seam class of thin strap-feet kept climbing one metal layer per patch until the geometry was changed architecturally: gapped risers, per-strap via1 descents into wide zone bands, and 16 µm met5 boundary planes answering a PROMOTE_LAYER directive.

Total: 3 loop + 4 builder iterations, minutes of tool time, REGRESSED list empty — for a cell class with no prior art in the flow. The v2 verdict is PASS with the residual 2.65× in the review band under sky130's labeled-estimate rules.

The tool polices itself

One more result, and for trust it may be the most important: an earlier analysis reported a "supply short" on DualCtrlVCO, confirmed by two "independent" methods — and same-day forensics overturned it. The rebuild was geometry-identical (layer-by-layer XOR empty), LVS matched 15 nets to 15, and 6534 of the cell's 6540 via3 cuts turned out to lie inside the MIM-capacitor top plate: any connectivity model without the capacitor plate layer turns every MIM cap into a plate-to-plate "short" — and both "independent" checks shared that same blind spot, so their agreement measured shared assumptions, not the layout. The tool was fixed the same day (MIM-aware connectivity), the detector was kept (it behaved correctly given its model), and the full post-mortem was published at the original finding's path — including the transferable lessons. A screening tool that documents its own false positive, with mechanism and fix, is the property that makes its positive findings worth acting on.

What this means for the next design

• Existing cells get regression protection. The gate rides every rebuild at 0.03–0.27 s, so a solved supply topology cannot silently regress — supply shorts, rail opens and single-cut supply vias block the build verdict the way a DRC error does.
• New cells start EM/IR-correct-by-construction. Accepted fixes become ledger lessons wired into the cell builders, and the curator's 430-directive harvest is already 57 builder-default patterns — the engine's next cell starts where the last campaign ended, and the repair loop fires less often over time.
• Every cell ships reliability evidence. Machine-readable EM/IR verdicts sit next to the DRC/LVS logs — corner-stamped report, directives, per-rectangle heat map — so "will the metal survive" has an auditable artifact at the moment the cell exists, not an IOU until chip assembly.

The honest ledger

Every number on this page comes from real runs with committed artifacts — reports, consoles, heat maps and before/after sidecars, each figure carrying its artifact path in the project's evidence trail. The ihp130 before/after outputs are open on GitHub: EMIR-Aware-Layout-Engine.

We at Si-Hive are passionate about AI and analog design — 40+ years of analog design experience and 5+ years in AI. We're looking for analog / mixed-signal / chip-design partners and pilots. Our flow runs today on open-source PDKs, and we're keen to bring it to your commercial or foundry PDK as a partner.